High coupling split-gate transistor and method for its formation

ABSTRACT

A split-gate transistor having high coupling for use in flash memory, EPROMs, and EEPROMs. The transistor has a U-shaped floating gate and a U-shaped control gate, thereby significantly increasing the surface area of the gates and increasing the voltage coupling ratio. The high coupling permits the operation voltage to be reduced while increasing operation speed, and the configuration of the transistor gates allows their use in high density arrays without sacrificing speed or degrading operations. A process for forming such transistors is also disclosed, wherein a polysilicon layer is deposited and then etched so that nitride and polysilicon spacers may be formed in between portions of polysilicon which are then etched to form floating gates. The nitride portion of the spacers is removed, and then the dielectric and control gate layers are formed on the floating gates to yield an array of split-gate transistors.

FIELD OF THE INVENTION

[0001] The present invention relates generally to an improvedsemiconductor structure for high density device arrays, and inparticular to an improved split-gate transistor having high coupling,and to a process for its formation.

BACKGROUND OF THE INVENTION

[0002] Nonvolatile semiconductor memory devices based onmetal-oxide-semiconductor field effect transistors (MOSFETs) arewell-known in the art. There are currently three general types of MOSFETnonvolatile memory devices in use: EPROMs, EEPROMs, and flash EEPROMs. Aflash EEPROM is comprised of an array of non-volatile storage cells fromwhich data may be read any number of times without disturbing the stateof the stored data. Each cell is an individual FET that stores a bit ofinformation as the presence or absence of an electrical charge on afloating gate.

[0003] Typically EEPROMs are comprised of an array of pairedtransistors: a select or access transistor and a storage transistor.Many flash EEPROMs combine these two transistors into one device—asplit-gate transistor with two gates sharing a single device channel.The control gate serves the function of the select or access transistor,and the floating gate serves as a storage device. The split-gateconfiguration alleviates the over-erase problem caused byFowler-Nordheim tunneling, but results in a larger cell size.

[0004] Data is typically written to a cell by hot electron injectionwhich occurs when a high positive voltage is applied to both the controlgate and the drain line. Some of the electrons in the device channelwill acquire sufficient energy to jump the energy barrier at theinterface of the device channel and the tunneling oxide. Once they arein the tunneling oxide, the electrons are pulled toward the floatinggate by the positive voltage on the control gate. This results in chargecollection on the floating gate, which in turn affects the thresholdvoltage of the control gate.

[0005] Alternatively, data may be written to a cell by Fowler-Nordheimtunneling, also called “cold electron” tunneling. Cold electrontunneling is a quantum-mechanical effect allowing electrons to passthrough, instead of over, the energy barrier at the interface of thedevice channel and the tunneling oxide. Because the electrons arepassing through the barrier, this process requires less energy than hotelectron injection, and can occur at a lower current density. Inaddition, use of Fowler-Nordheim tunneling for both programming anderasing enables operation voltages and power consumption to be reduced.

[0006] The cells are read by addressing the control gate and drain lineof a cell with a positive voltage (e.g., 3 to 5 volts). If the floatinggate is negatively charged (logical state “1”), the threshold voltagewill be high and the cell device will not turn on when addressed. If thefloating gate is uncharged (logical state “0”), the threshold voltagewill be low, and the device channel will invert when addressed, causinga resulting current in the drain line that can be sensed by currentsensing methods known in the art.

[0007] Erasure is accomplished by Fowler-Nordheim tunneling. A highvoltage (e.g. 10 volts) is applied between the control gate and thesource, causing electrons to leave the floating gate and tunnel throughthe tunneling oxide to the drain. Any individual cell or all cells maybe simultaneously erased by applying an electrical pulse to any or allcells.

[0008] The easy reprogrammability, inherent short access time andnon-volatility of the stored data make flash memory very attractive formany computer applications. Advancements in semiconductor fabricationtechnology have enabled the formation of denser and smaller memoryarrays by decreasing the size of individual devices. Decreased devicesize has a cost, however, that is especially noticeable for split-gatetransistors. Reduction in the size of the floating gate reduces thecoupling ratio, resulting in slower operation speeds and degradation ofprogramming and erase operations. In addition, devices with low couplingratios require higher voltages for operation, an undesirablecharacteristic for many applications such as portable systems.

[0009] There is needed, therefore, a split-gate transistor exhibitinghigh coupling for use in device arrays such as flash memory arrays. Asimple method of fabricating a high coupling split-gate transistor isalso needed.

SUMMARY OF THE INVENTION

[0010] The present invention provides a split-gate transistor havinghigh coupling due to the U-shaped configuration of the floating andcontrol gates. Also provided is a method for its formation, in which afirst polysilicon layer is formed on a substrate and then a plurality ofnitride spacers are formed to divide the first polysilicon layer intoindividual floating gates. A plurality of polysilicon spacers are formedon top of the nitride spacers, which are then removed. Dielectric andcontrol gate layers are then deposited. The resultant U-shapedconfiguration of the gates allows for a high coupling, therebyincreasing the speed of the device while lowering the operation voltageand increasing the device density.

[0011] Additional advantages and features of the present invention willbe apparent from the following detailed description and drawings whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a perspective view of the split-gate transistor of thepresent invention.

[0013]FIG. 2 is a cross-sectional view of the transistor of FIG. 1.

[0014]FIG. 3 is a cross-sectional view of a semiconductor waferundergoing the process of a preferred embodiment.

[0015]FIG. 4 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 3.

[0016]FIG. 5 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 4.

[0017]FIG. 6 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 5.

[0018]FIG. 7 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 6.

[0019]FIG. 8 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 7.

[0020]FIG. 9 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 8.

[0021]FIG. 10 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 9.

[0022]FIG. 11 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 10.

[0023]FIG. 12 shows the wafer of FIG. 3 at a processing step subsequentto that shown in FIG. 11.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0024] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0025] The terms “wafer” and “substrate” are to be understood asincluding silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium arsenide. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

[0026] Referring now to the drawings, where like elements are designatedby like reference numerals, an embodiment of the device array 20 of thepresent invention is shown in FIGS. 1 and 2. The device array 20 iscomprised of a plurality of split-gate transistors 22 formed on asubstrate 24, where the split-gate transistors 22 are separated fromeach other by isolation bars 26. Each split-gate transistor 22 comprisestwo gates, a floating gate 30 and a control gate 34, which areself-aligned with the device channel 28. The floating gate 30 andcontrol gate 34 may be formed of polysilicon, tungsten silicide, orother suitable conductive material, and have a thickness within therange of 200 to 1500 Angstroms, preferably about 500 Angstroms.

[0027] The device channel 28 is overlain by a tunneling oxide layer 36comprised of thermal oxide, and having a thickness of approximately 50to 110 Angstroms thick. Preferably the tunneling oxide 36 is about 80Angstroms thick. On top of the tunneling oxide 36 is the floating gate30. A dielectric layer 32 is formed on top of the floating gate 30, andserves to insulate the floating gate 30 from the control gate 34. Thedielectric layer 32 is approximately 70 to 180 Angstroms thick, and ispreferably about 120 to 140 Angstroms thick, and may be formed of asuitable dielectric material or materials, such as ONO(oxide-nitride-oxide), ON (oxide-nitride) or oxide. The control gate 34lies on top of the dielectric layer 32, forming the top layer of thesplit-gate transistor 22. Each split-gate transistor 22 also has dopedsource and drain regions 38,40. As shown in FIG. 2, an insulating layer42 of silicon dioxide, BSG, PSG, BPSG, or the like may cover the entiresurface of the array 20.

[0028] Data is written to a split-gate transistor 22 by hot electroninjection or Fowler-Nordheim tunneling, which occur when a high positivevoltage is applied to both the control gate 34 and the drain 40. Thetransistors 22 are read by addressing the control gate 34 with apositive voltage (e.g., 3 to 5 volts). Erasure is accomplished byFowler-Nordheim tunneling, which occurs when a high voltage (e.g. 10volts) is applied between the control gate 34 and the source 38, causingelectrons to leave the floating gate 30 and tunnel through the tunnelingoxide 36 to the source 38.

[0029] The split-gate transistor 22 of the present invention has a highcoupling ratio due to its U-shaped gates. Compared to a conventionalflat floating gate, the floating gate 30, dielectric layer 32, and thecontrol gate 34 have increased surface areas due to their generallyU-shaped configuration. This increased surface area increases thecapacitance of each layer, resulting in high coupling, as shown in thefollowing equation, where C_(D) represents the capacitance of thedielectric layer 32, and C_(tun) represents the capacitance of thetunneling oxide layer 36: coupling=C_(D)/(C_(D)+C_(tun)). Because of itshigh coupling, the split-gate transistor 22 has increased programmingand erase speeds, and a reduced operation voltage. In addition, theU-shaped configuration of the floating gate 30 expands the surface areaby increasing the size of the floating gate in the vertical direction,thereby preserving a relatively small gate (in the horizontal direction)and maintaining or increasing array density.

[0030] The device array 20 is manufactured through a process describedas following, and illustrated by FIGS. 3 through 12. First, a substrate24, which may be any of the types of substrate described above, isselected as the base for the device array 20. The substrate 24 may bedoped or undoped, but a p-type doped wafer is preferred. If PMOS devicesare to be formed, photolithography is used to define areas where n-wells(not shown) are implanted. The level of doping in the n-wells may varybut should be of comparable or greater strength than the doping level ofthe substrate 24.

[0031] As shown in FIG. 3, isolation bars 26 are formed prior to theformation of the split-cell transistors. These bars 26 may be formed byany known technique such as thermal oxidation of the underlyingsubstrate 24 in a LOCOS process or by etching trenches and filling themwith oxide in an STI process. Source and drain regions 38,40 are alsoformed at this time. The first step in the process of forming thetransistors 22 is the growth of a tunneling oxide layer 36, which isapproximately 50 to 110 Angstroms thick, on top of the substrate 24 bymeans such as thermal oxidation or chemical vapor deposition (CVD).Preferably the tunneling oxide layer 36 is approximately 70 to 100Angstroms thick, and most preferable is approximately 80 Angstromsthick.

[0032]FIG. 4 depicts the next step in the process, which is thedeposition of a thick polysilicon layer 50 over the surface of the array20. The layer 50 has a thickness within the range of 2000 to 3000Angstroms, preferably 2250 to 2750 Angstroms, and most preferably isapproximately 2500 Angstroms. The layer 50 is formed by CVD, plasmadeposition, or other suitable means.

[0033] Trenches 52 are then formed in the polysilicon layer 50, as shownin FIG. 5. A resist and mask (not shown) are applied, and suitableremoval techniques are used to form trenches 52 approximately 0.15 to0.25 microns wide over the isolation bars 26, in a direction orthogonalto the direction of the source and drain lines. Suitable removaltechniques include wet etching using an acid such as nitric and/orhydrofluoric acid, or dry etching methods such as plasma etching orreactive ion etching (RIE).

[0034] Referring now to FIG. 6, nitride spacers 54 are formed in thetrenches 52 by deposition of silicon nitride (Si₃N₄) over the surface ofthe array 20. The nitride may be deposited by CVD, plasma deposition, orother suitable means to a thickness of approximately 3500 to 5000Angstroms. Following deposition, excess nitride is then removed via anetchback procedure, such as wet etching with hot phosphoric acid, or dryetching, or via planarization of the array 20 using chemical-mechanicalpolishing (CMP) or the like. The resultant structure is shown in FIG. 6.

[0035]FIG. 7 illustrates the etchback of the polysilicon layer 50 toform a thinner polysilicon layer 50. The etchback is performed bysuitable etching techniques such as wet etching with nitric and/orhydrofluoric acid, plasma etching, or RIE. The resultant polysiliconlayer 50 has a thickness of approximately 200 to 1000 Angstroms,preferably about 500 Angstroms.

[0036] As shown in FIG. 8, the next step is the formation of apolysilicon spacer layer 56 on top of the polysilicon layer 50. Thepolysilicon spacer layer 56 has a thickness within the range of 300 to1000 Angstroms, preferably about 500 Angstroms. The layer 56 is formedby CVD, plasma deposition, or other suitable means.

[0037] The polysilicon spacer layer is then etched back by plasmaetching or the like to leave small portions of the polysilicon spacerlayer 56 on the polysilicon layer 50, as shown in FIG. 9. FIG. 10illustrates the next step of the process, in which the nitride spacers54 are removed. Removal may be accomplished by wet etching using hotphosphoric acid or another suitable etchant, or by dry etching. Thepolysilicon layer 50 and the wedge-shaped portions of the polysiliconspacer layer 56 that remained after etchback in FIG. 9 are shown asindividual floating gates 30 in FIG. 10.

[0038] As shown in FIG. 11, the next step is the formation of adielectric layer 32 on top of the floating gates 30. The dielectriclayer 32 may be formed by means known in the art, e.g., if the layer isan ONO layer, the nitride layer may be formed by CVD, and the oxidelayers may be formed by CVD or by thermal oxidation. The dielectriclayer 32 has a thickness within the range of approximately 70 to 180Angstroms, preferably 120 to 140 Angstroms, and most preferably 130Angstroms.

[0039] The next step in the process is the deposition of a thickpolysilicon layer 60 over the array 20, as shown in FIG. 12. The layer60 has a thickness within the range of 2000 to 3000 Angstroms,preferably 2250 to 2750 Angstroms, and most preferably is approximately2500 Angstroms. The layer 60 is formed by CVD, plasma deposition, orother suitable means. Plasma etching is now performed to etch back thepolysilicon layer 60 to form control gates 34 having a thickness ofapproximately 300 to 1000 Angstroms, preferably about 500 Angstroms.

[0040] The split-gate transistor 22 is essentially complete at thisstage, and conventional processing methods may then be used to formcontacts and wiring to connect gate lines and other connections in thearray 20. For example, the entire surface of the array 20 may be coveredwith a passivation layer of, e.g., silicon dioxide, BSG, PSG, or BPSG,which is CMP planarized and etched to provide contact holes, which maythen be metallized to provide contacts to the transistor gates.

[0041] As can be seen by the embodiments described herein, the presentinvention encompasses split-gate transistors having U-shaped floatinggates, thereby significantly increasing the surface area of the floatinggates. As may be readily appreciated by persons skilled in the art, thisincreased surface area provides an increase in the effective capacitancebetween the control gate and the floating gate for each transistor. As aresult, the voltage coupling ratio is improved, and the operation speedof the device is significantly enhanced.

[0042] The above description and drawings illustrate preferredembodiments which achieve the objects, features and advantages of thepresent invention. It is not intended that the present invention belimited to the illustrated embodiments. Any modification of the presentinvention which comes within the spirit and scope of the followingclaims should be considered part of the present invention.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of forming a split-gate transistor,comprising the steps of: forming a first polysilicon layer on asubstrate which has a plurality of isolation bars formed therein;forming a plurality of nitride spacers, wherein each spacer is formedover one of the isolation bars, and wherein the plurality of spacersdivides the first polysilicon layer into at least one floating gate;forming a plurality of polysilicon spacers on the nitride spacers;removing the plurality of nitride spacers; forming a dielectric layer onthe at least one floating gate; and forming a second polysilicon layeron the dielectric layer, wherein the plurality of spacers divides thesecond polysilicon layer into at least one control gate.
 2. The methodof claim 1, further comprising forming source and drain regions in thesubstrate in a direction orthogonal to said plurality of nitridespacers.
 3. The method of claim 1, further comprising forming atunneling oxide layer on the substrate prior to said step of forming afirst polysilicon layer.
 4. The method of claim 1, wherein said step offorming a first polysilicon layer comprises chemical vapor deposition.5. The method of claim 1, wherein said step of forming a firstpolysilicon layer comprises plasma deposition.
 6. The method of claim 1,wherein said step of forming a plurality of nitride spacers comprisesdefining trenches in the first polysilicon layer and filling thetrenches with nitride.
 7. The method of claim 1, wherein the at leastone floating gate has a thickness of approximately 200 to 1000Angstroms.
 8. The method of claim 1, wherein the at least one floatinggate has a thickness of approximately 500 Angstroms.
 9. The method ofclaim 1, wherein the dielectric layer is a layer of ONO.
 10. The methodof claim 9, wherein said step of forming a dielectric layer comprisesformation of a first oxide layer, deposition of a nitride layer, andformation of a second oxide layer.
 11. The method of claim 10, whereinsaid step of forming a first oxide layer comprises thermal oxidation.12. The method of claim 10, wherein said step of forming a first oxidelayer comprises chemical vapor deposition.
 13. The method of claim 10,wherein said step of forming a second oxide layer comprises thermaloxidation.
 14. The method of claim 10, wherein said step of forming asecond oxide layer comprises chemical vapor deposition.
 15. The methodof claim 1, wherein the dielectric layer is a layer of ON.
 16. Themethod of claim 1, wherein the dielectric layer is a layer of oxide. 17.The method of claim 1, wherein the dielectric layer has a thicknesswithin the range of approximately 70 to 180 Angstroms.
 18. The method ofclaim 1, wherein the dielectric layer has a thickness within the rangeof approximately 120 to 140 Angstroms.
 19. The method of claim 1,wherein the dielectric layer has a thickness of approximately 130Angstroms.
 20. The method of claim 1, wherein said step of forming asecond polysilicon layer comprises chemical vapor deposition.
 21. Themethod of claim 1, wherein said step of forming a second polysiliconlayer comprises plasma deposition.
 22. The method of claim 1, furthercomprising plasma etching of the second polysilicon layer to form the atleast one control gate after said step of forming a second polysiliconlayer.
 23. The method of claim 1, wherein the at least one control gatehas a thickness of approximately 300 to 1000 Angstroms.
 24. The methodof claim 1, wherein the at least one control gate has a thickness ofapproximately 500 Angstroms.
 25. The method of claim 1, wherein saidstep of removing the plurality of nitride spacers comprises wet etching.26. The method of claim 1, wherein said step of removing the pluralityof nitride spacers comprises dry etching.
 27. A method of formingsplit-gate transistors, comprising the steps of: providing a substratewhich has a plurality of isolation bars formed therein; forming atunneling oxide layer on the substrate between the isolation bars;forming a first polysilicon layer on the tunneling oxide layer; forminga plurality of nitride spacers, wherein each spacer is formed over oneof the isolation bars, and wherein the plurality of spacers divides thefirst polysilicon layer into a plurality of U-shaped floating gates;forming a plurality of polysilicon spacers on the nitride spacers;removing the plurality of nitride spacers; forming a dielectric layer onthe floating gates; and forming a second polysilicon layer on thedielectric layer, wherein the plurality of spacers divides the secondpolysilicon layer into a plurality of U-shaped control gates.
 28. Themethod of claim 27, wherein said step of forming a tunneling oxide layercomprises thermal oxidation.
 29. The method of claim 27, wherein saidstep of forming a tunneling oxide layer comprises chemical vapordeposition.
 30. The method of claim 27, wherein the tunneling oxidelayer has a thickness within the range of approximately 50 to 110Angstroms.
 31. The method of claim 27, wherein the tunneling oxide layerhas a thickness within the range of approximately 70 to 100 Angstroms.32. The method of claim 27, wherein the tunneling oxide layer has athickness of approximately 80 Angstroms.
 33. The method of claim 27,further comprising forming source and drain regions in the substrate ina direction orthogonal to said plurality of nitride spacers.
 34. Themethod of claim 27, wherein said step of forming a first polysiliconlayer comprises chemical vapor deposition.
 35. The method of claim 27,wherein said step of forming a first polysilicon layer comprises plasmadeposition.
 36. The method of claim 27, wherein said step of forming aplurality of nitride spacers comprises defining trenches in the firstpolysilicon layer and filling the trenches with nitride.
 37. The methodof claim 27, wherein the floating gates have a thickness ofapproximately 200 to 1000 Angstroms.
 38. The method of claim 27, whereinthe floating gates have a thickness of approximately 500 Angstroms. 39.The method of claim 27, wherein the dielectric layer is a layer of ONO.40. The method of claim 39, wherein said step of forming a dielectriclayer comprises formation of a first oxide layer, deposition of anitride layer, and formation of a second oxide layer.
 41. The method ofclaim 27, wherein the dielectric layer is a layer of ON.
 42. The methodof claim 27, wherein the dielectric layer is a layer of oxide.
 43. Themethod of claim 27, wherein the dielectric layer has a thickness withinthe range of approximately 120 to 140 Angstroms.
 44. The method of claim27, wherein the dielectric layer has a thickness of approximately 130Angstroms.
 45. The method of claim 27, wherein said step of forming asecond polysilicon layer comprises chemical vapor deposition.
 46. Themethod of claim 27, further comprising plasma etching of the secondpolysilicon layer to form the plurality of U-shaped control gates aftersaid step of forming a second polysilicon layer.
 47. The method of claim27, wherein the control gates have a thickness of approximately 300 to1000 Angstroms.
 48. The method of claim 27, wherein the control gateshave a thickness of approximately 500 Angstroms.
 49. A method of formingsplit-gate transistors, comprising the steps of: forming a firstpolysilicon layer on a substrate which has a plurality of isolation barsformed therein; forming a plurality of trenches in the first polysiliconlayer, wherein each trench is formed over one of the isolation bars in adirection parallel to the bars; forming a plurality of nitride spacersby filling the plurality of trenches with nitride, wherein the pluralityof spacers divides the first polysilicon layer into a plurality ofU-shaped floating gates; forming a plurality of polysilicon spacers onthe nitride spacers; removing the plurality of nitride spacers; forminga dielectric layer on the floating gates; and forming a secondpolysilicon layer on the dielectric layer, wherein the plurality ofspacers divides the second polysilicon layer into a plurality ofU-shaped control gates.
 50. The method of claim 49, further comprisingforming source and drain regions in the substrate in a directionorthogonal to said plurality of nitride spacers.
 51. The method of claim49, further comprising forming a tunneling oxide layer on the substrateprior to said step of forming a first polysilicon layer.
 52. The methodof claim 49, wherein said step of forming a plurality of trenchescomprises defining the plurality of trenches using photolithography, andsubsequently removing portions of the first polysilicon layer to formthe plurality of trenches.
 53. The method of claim 52, wherein saidremoval step comprises wet etching.
 54. The method of claim 52, whereinsaid removal step comprises plasma etching.
 55. The method of claim 52,wherein said removal step comprises reactive ion etching.
 56. The methodof claim 49, wherein said step of forming a plurality of nitride spacerscomprises chemical vapor deposition.
 57. The method of claim 49, whereinsaid step of forming a plurality of nitride spacers comprises plasmadeposition.
 58. The method of claim 49, wherein said step of forming aplurality of polysilicon spacers further comprises etching of the firstpolysilicon layer to form the plurality of U-shaped floating gates. 59.The method of claim 58, wherein said etching step comprises wet etching.60. The method of claim 58, wherein said etching step comprises plasmaetching.
 61. The method of claim 58, wherein said etching step comprisesreactive ion etching.
 62. The method of claim 58, wherein the firstpolysilicon layer has a thickness within the range of 2000 to 3000Angstroms.
 63. The method of claim 58, wherein the first polysiliconlayer has a thickness within the range of 2250 to 2750 Angstroms. 64.The method of claim 58, wherein the first polysilicon layer has athickness of approximately 2500 Angstroms.
 65. The method of claim 49,wherein the floating gates have a thickness of approximately 200 to 1000Angstroms.
 66. The method of claim 49, wherein the floating gates have athickness of approximately 500 Angstroms.
 67. The method of claim 49,wherein said step of forming a second polysilicon layer furthercomprises plasma etching of the second polysilicon layer to form theplurality of U-shaped control gates.
 68. The method of claim 67, whereinthe second polysilicon layer has a thickness within the range of 2000 to3000 Angstroms.
 69. The method of claim 67, wherein the secondpolysilicon layer has a thickness within the range of 2250 to 2750Angstroms.
 70. The method of claim 67, wherein the second polysiliconlayer has a thickness of approximately 2500 Angstroms.
 71. The method ofclaim 49, wherein the control gates have a thickness of approximately300 to 1000 Angstroms.
 72. The method of claim 49, wherein the controlgates have a thickness of approximately 500 Angstroms.
 73. The method ofclaim 49, further comprising formation of a passivation layer over thesecond polysilicon layer after the control gates have been formed. 74.The method of claim 73, wherein the passivation layer is a layer ofsilicon dioxide.
 75. The method of claim 73, wherein the passivationlayer is a layer of glass selected from the group consisting of BSG,PSG, and BPSG.